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(parent: f1fd8a9) | patch
drm/amd/display: Revert "correct sw cache timing to ensure dispclk ramping"
authorCharlene Liu <Charlene.Liu@amd.com>
Fri, 12 Sep 2025 16:37:30 +0000 (12:37 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 23 Sep 2025 14:32:33 +0000 (10:32 -0400)
commit550038edef7f933591e10e32f94a5e9557b023b8
tree3d150ff32fa05374100c1bc393d14c726c6079f8tree | snapshot
parentf1fd8a9ac2aa5118f76baf28e6ca4d6962a485becommit | diff
drm/amd/display: Revert "correct sw cache timing to ensure dispclk ramping"

[why]
Need consider SSC enabled case

This reverts commit f1fd8a9ac2aa5118f76baf28e6ca4d6962a485be.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Reviewed-by: Chris Park <chris.park@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c diff | blob | blame | history
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