RISC-V: Enable select_vl for RVV auto-vectorization

RISC-V: Enable select_vl for RVV auto-vectorization

Consider this following example:
void vec_add(int32_t *restrict c, int32_t *restrict a, int32_t *restrict b,
             int N) {
  for (long i = 0; i < N; i++) {
    c[i] = a[i] + b[i];
  }
}

After this patch:
vec_add:
        ble     a3,zero,.L5
.L3:
        vsetvli a5,a3,e32,m1,ta,ma
        vle32.v v2,0(a1)
        vle32.v v1,0(a2)
        vsetvli a6,zero,e32,m1,ta,ma ===> redundant vsetvl.
        slli    a4,a5,2
        vadd.vv v1,v1,v2
        sub     a3,a3,a5
        vsetvli zero,a5,e32,m1,ta,ma ===> redundant vsetvl.
        vse32.v v1,0(a0)
        add     a1,a1,a4
        add     a2,a2,a4
        add     a0,a0,a4
        bne     a3,zero,.L3
.L5:
        ret

We can get close-to-optimal codegen but with some redundant vsetvls.
This is not the big issue which will be easily addressed in RISC-V backend.

I am going to add a standalone PASS "AVL propagation" (avlprop) to addresse
such issue.

gcc/ChangeLog:

	* config/riscv/autovec.md (select_vl<mode>): New pattern.
	* config/riscv/riscv-protos.h (expand_select_vl): New function.
	* config/riscv/riscv-v.cc (expand_select_vl): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: New test.