RISC-V: Support RVV VFCVT.XU.F.V rounding mode intrinsic API

RISC-V: Support RVV VFCVT.XU.F.V rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFCVT.XU.F.V as the below samples.

* __riscv_vfcvt_xu_f_v_u32m1_rm
* __riscv_vfcvt_xu_f_v_u32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(BASE): New declaration.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfcvt_xu_frm): New intrinsic function def..

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-cvt-xu.c: New test.