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dt-bindings: riscv: cpus: Add SiFive X280 compatible
authorDrew Fustini <dfustini@oss.tenstorrent.com>
Tue, 14 Oct 2025 03:11:55 +0000 (20:11 -0700)
committerDrew Fustini <dfustini@oss.tenstorrent.com>
Sat, 18 Oct 2025 17:44:14 +0000 (10:44 -0700)
commit571e42a1197c432d6bb78e1feb9586b4feb0a981
tree83f0e22ca4609146004f5fa99ceab46491a7b0a1tree
parent4de28f1edcfbd22ade0a69b97a10a43d09f5d4b4commit | diff
dt-bindings: riscv: cpus: Add SiFive X280 compatible

Document compatible for the SiFive X280 RISC-V core.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com>
Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>
Documentation/devicetree/bindings/riscv/cpus.yaml diff | blob | blame | history
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