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riscv: dts: starfive: fml13v01: enable pcie1
authorSandie Cao <sandie.cao@deepcomputing.io>
Fri, 7 Feb 2025 09:36:18 +0000 (17:36 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Tue, 18 Feb 2025 16:28:33 +0000 (16:28 +0000)
commit57b5369f36686961bebddc98d894d095d0b402a8
tree2318b42a729f3b51bdf5e04ac99fa37e6323be91tree
parent4bdea6e33946d481d54f6903b716101dd75b884ecommit | diff
riscv: dts: starfive: fml13v01: enable pcie1

Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.

Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
Tested-by: Maud Spierings <maud_spierings@hotmail.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git