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(parent: fb495a5) | patch
drm/msm/a8xx: Fix RSCC offset
authorAkhil P Oommen <akhilpo@oss.qualcomm.com>
Fri, 22 May 2026 10:11:57 +0000 (15:41 +0530)
committerRob Clark <robin.clark@oss.qualcomm.com>
Fri, 29 May 2026 14:07:27 +0000 (07:07 -0700)
commit586a34dafc08c4fa68d1b4673de24cd84d09df05
treea9a6a54adfc74a530d39ca15f53bc5e065037e7etree | snapshot
parentfb495a57d66e791144ad1da898914b97a87853d6commit | diff
drm/msm/a8xx: Fix RSCC offset

In A8xx, the RSCC block is part of GPU's register space. Update the
virtual base address of rscc to point to the correct address.

Fixes: 50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x GMU")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/727117/
Message-ID: <20260522-glymur-gpu-dt-v5-1-562c406b210c@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
drivers/gpu/drm/msm/adreno/a6xx_gmu.c diff | blob | blame | history
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