RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688]

RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688]

This patch would like to fix the wroing code generation for the scalar
signed SAT_TRUNC.  The input can be QI/HI/SI/DI while the alu like sub
can only work on Xmode.  Unfortunately we don't have sub/add for
non-Xmode like QImode in scalar, thus we need to sign extend to Xmode
to ensure we have the correct value before ALU like add.  The gen_lowpart
will generate something like lbu which has all zero for highest bits.

For example, when 0xff7f(-129 for HImode) trunc to QImode, we actually
want compare -129 to -128, but if there is no sign extend like lbu, we will
compare 0xff7f to 0xffffffffffffff80(assum Xmode is DImode).  Thus, we have
to sign extend 0xff(Qmode) to 0xffffffffffffff7f(assume Xmode is DImode)
before compare in Xmode.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

	PR target/117688

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_sstrunc): Leverage the helper
	riscv_extend_to_xmode_reg with SIGN_EXTEND.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/pr117688.h: Add test helper macros.
	* gcc.target/riscv/pr117688-trunc-run-1-s16-to-s8.c: New test.
	* gcc.target/riscv/pr117688-trunc-run-1-s32-to-s16.c: New test.
	* gcc.target/riscv/pr117688-trunc-run-1-s32-to-s8.c: New test.
	* gcc.target/riscv/pr117688-trunc-run-1-s64-to-s16.c: New test.
	* gcc.target/riscv/pr117688-trunc-run-1-s64-to-s32.c: New test.
	* gcc.target/riscv/pr117688-trunc-run-1-s64-to-s8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>