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(parent: 5dfcaec) | patch
drm/amd/display: Add FRL registers for DCN321
authorRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Fri, 19 May 2023 00:24:02 +0000 (18:24 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 11 May 2026 20:15:11 +0000 (16:15 -0400)
commit5bad9d8a1e70667be030dceb06257f472407777a
tree1b345c8fecbb37d8e5ab477d6d7c2085a26ab04ftree | snapshot
parent5dfcaecc7e1f7cd54134b093993aa3449e79afaecommit | diff
drm/amd/display: Add FRL registers for DCN321

Add the required DCN3.2.1 registers to enable FRL in this ASIC.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h diff | blob | blame | history
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h diff | blob | blame | history
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