aarch64: Relax FP/vector register matches

aarch64: Relax FP/vector register matches

There were many tests that used [0-9] to match an FP or vector register,
but that should allow any of 0-31 instead.

asm-x-constraint-1.c required s0-s7, but that's the range for "y"
rather than "x".  "x" allows s0-s15.

sve/pcs/return_9.c required z2-z7 (the initial set of available
call-clobbered registers), but z24-z31 are OK too.

gcc/testsuite/
	* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c: Allow any
	FP/vector register, not just register 0-9.
	* gcc.target/aarch64/fmul_fcvt_2.c: Likewise.
	* gcc.target/aarch64/ldp_stp_8.c: Likewise.
	* gcc.target/aarch64/ldp_stp_17.c: Likewise.
	* gcc.target/aarch64/ldp_stp_21.c: Likewise.
	* gcc.target/aarch64/simd/vpaddd_f64.c: Likewise.
	* gcc.target/aarch64/simd/vpaddd_s64.c: Likewise.
	* gcc.target/aarch64/simd/vpaddd_u64.c: Likewise.
	* gcc.target/aarch64/sve/adr_1.c: Likewise.
	* gcc.target/aarch64/sve/adr_2.c: Likewise.
	* gcc.target/aarch64/sve/adr_3.c: Likewise.
	* gcc.target/aarch64/sve/adr_4.c: Likewise.
	* gcc.target/aarch64/sve/adr_5.c: Likewise.
	* gcc.target/aarch64/sve/extract_1.c: Likewise.
	* gcc.target/aarch64/sve/extract_2.c: Likewise.
	* gcc.target/aarch64/sve/extract_3.c: Likewise.
	* gcc.target/aarch64/sve/extract_4.c: Likewise.
	* gcc.target/aarch64/sve/slp_4.c: Likewise.
	* gcc.target/aarch64/sve/spill_3.c: Likewise.
	* gcc.target/aarch64/vfp-1.c: Likewise.
	* gcc.target/aarch64/asm-x-constraint-1.c: Allow s0-s15, not just
	s0-s7.
	* gcc.target/aarch64/sve/pcs/return_9.c: Allow z24-z31 as well as
	z2-z7.