RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit

RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit

[ Upstream commit ea6398a5af81e3e7fb3da5d261694d479a321fd9 ]

This doesn't cause a problem currently as HVIEN isn't used elsewhere
yet. Found by inspection.

Signed-off-by: Michael Neuling <michaelneuling@tenstorrent.com>
Fixes: 16b0bde9a37c ("RISC-V: KVM: Add perf sampling support for guests")
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20241127041840.419940-1-michaelneuling@tenstorrent.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>