drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup

drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup

Define the C10 PLL SSC register range via macros, so the HW/SW state of
these register can be verified by a follow-up change, reusing these
macros.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-10-mika.kahola@intel.com