Disparages SSE_REGS alternatives sligntly with ?v instead of *v in *mov{si,di}_internal.

Disparages SSE_REGS alternatives sligntly with ?v instead of *v in *mov{si,di}_internal.

So alternative v won't be igored in record_reg_classess.

Similar for *r alternatives in some vector patterns.

It helps testcase in the PR, also RA now makes better decisions for
gcc.target/i386/extract-insert-combining.c

        movd    %esi, %xmm0
        movd    %edi, %xmm1
-       movl    %esi, -12(%rsp)
        paddd   %xmm0, %xmm1
        pinsrd  $0, %esi, %xmm0
        paddd   %xmm1, %xmm0

The patch has no big impact on SPEC2017 for both O2 and Ofast
march=native run.

And I noticed there's some changes in SPEC2017 from code like

mov mem, %eax
vmovd %eax, %xmm0
..
mov %eax, 64(%rsp)

to

vmovd mem, %xmm0
..
vmovd %xmm0, 64(%rsp)

Which should be exactly what we want?

gcc/ChangeLog:

	PR target/105513
	PR target/105504
	* config/i386/i386.md (*movsi_internal): Change alternative
	from *v to ?v.
	(*movdi_internal): Ditto.
	* config/i386/sse.md (vec_set<mode>_0): Change alternative *r
	to ?r.
	(*vec_extractv4sf_mem): Ditto.
	(*vec_extracthf): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr105513-1.c: New test.
	* gcc.target/i386/extract-insert-combining.c: Add new
	scan-assembler-not for spill.