]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1
authorPan Li <pan2.li@intel.com>
Tue, 13 May 2025 14:38:57 +0000 (22:38 +0800)
committerPan Li <pan2.li@intel.com>
Fri, 16 May 2025 07:54:27 +0000 (15:54 +0800)
commit5f523f6255cc48643adab431839557dc3d73d70f
tree057b94c85ccc38c4934d38dc73dc45f7a18f1e1a
parent621cb3dc9996a160e3e65bce4a8e61da26caafa7
RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1

Add asm dump check test for vec_duplicate + vsub.vv combine to vsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Add test cases
for vsub vx combine case 1 with GR2VR cost 1.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c