RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.

Form 12:
  #define DEF_SAT_U_SUB_FMT_12(T)                        \
  T __attribute__((noinline))                            \
  sat_u_sub_##T##_fmt_12 (T x, T y)                      \
  {                                                      \
    T ret;                                               \
    bool overflow = __builtin_sub_overflow (x, y, &ret); \
    return !overflow ? ret : 0;                          \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add helper macro for
	testing.
	* gcc.target/riscv/sat_u_sub-45.c: New test.
	* gcc.target/riscv/sat_u_sub-46.c: New test.
	* gcc.target/riscv/sat_u_sub-47.c: New test.
	* gcc.target/riscv/sat_u_sub-48.c: New test.
	* gcc.target/riscv/sat_u_sub-run-45.c: New test.
	* gcc.target/riscv/sat_u_sub-run-46.c: New test.
	* gcc.target/riscv/sat_u_sub-run-47.c: New test.
	* gcc.target/riscv/sat_u_sub-run-48.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>