RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on GR2VR cost

RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vwaddu.vv to the
vwaddu.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

Before this patch:
  11       beq a3,zero,.L8
  12       vsetvli a5,zero,e32,m1,ta,ma
  13       vmv.v.x v2,a2
  ...
  16   .L3:
  17       vsetvli a5,a3,e32,m1,ta,ma
  ...
  22       vwaddu.vv v1,v2,v3
  ...
  25       bne a3,zero,.L3

After this patch:
  11       beq a3,zero,.L8
  ...
  14    .L3:
  15       vsetvli a5,a3,e32,m1,ta,ma
  ...
  20       vwaddu.vx v1,a2,v3
  ...
  23       bne a3,zero,.L3

The pattern of this patch only works on DImode, aka below pattern.
v1:RVVM1DImode = (zero_extend:RVVM1DImode v2:RVVM1SImode)
  + (vec_dup:RVVM1DImode (zero_extend:DImode x2:SImode));

Unfortunately, for uint16_t to uint32_t or uint8_t to uint16_t, we loss
this extend op after expand.

For uint16_t => uint32_t we have:
(set (reg:SI 149) (subreg/s/v:SI (reg/v:DI 146 [ rs1 ]) 0))

For uint32_t => uint64_t we have:
(set (reg:DI 148 [ _6 ])
     (zero_extend:DI (subreg/s/u:SI (reg/v:DI 146 [ rs1 ]) 0)))

We can see there is no zero_extend for uint16_t to uint32_t, and we
cannot hit the pattern above.  So the combine will try below pattern
for uint16_t to uint32_t.

v1:RVVM1SImode = (zero_extend:RVVM1SImode v2:RVVM1HImode)
  + (vec_dup:RVVM1SImode (subreg:SIMode (:DImode x2:SImode)))

But it cannot match the vwaddu sematics, thus we need another handing
for the vwaddu.vv for uint16_t to uint32_t, as well as the uint8_t to
uint16_t.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*widen_first_<any_extend:su>_vx_<mode>):
	Add helper bridge pattern for vwaddu.vx combine.
	(*widen_<any_widen_binop:optab>_<any_extend:su>_vx_<mode>): Add
	new pattern to match vwaddu.vx combine.
	* config/riscv/iterators.md: Add code attr to get extend CODE.
	* config/riscv/vector-iterators.md: Add Dmode iterator for
	widen.

Signed-off-by: Pan Li <pan2.li@intel.com>