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PowerPC: Optimized isnan/isnanf for POWER8
authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Thu, 27 Feb 2014 15:43:51 +0000 (09:43 -0600)
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Mon, 3 Mar 2014 16:41:46 +0000 (10:41 -0600)
commit65c8daedb68b74eae860f91dca226215cd80e348
tree145fc2a4273cf6e57ab17835d3fb9008af09784ftree
parent55e71ccf31c29a7839344f03e0a7437ea0f5f211commit | diff
PowerPC: Optimized isnan/isnanf for POWER8

This patch add a optimized isnan/isnanf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

Backport of 487972aea52004f604c2878c8c9d3e77670f2c32
ChangeLog diff | blob | blame | history
sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h diff | blob | blame | history
sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile diff | blob | blame | history
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isnan-power8.S [new file with mode: 0644] blob
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isnan.c diff | blob | blame | history
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isnanf.c diff | blob | blame | history
sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S [new file with mode: 0644] blob
sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S [new file with mode: 0644] blob
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