[RISC-V] Clear both upper and lower bits using 3 shifts

[RISC-V] Clear both upper and lower bits using 3 shifts

So the next step in Shreya's work.  In the prior patch we used two shifts to
clear bits at the high or low end of an object.  In this patch we use 3 shifts
to clear bits on both ends.

Nothing really special here.  With mvconst_internal still in the tree it's of
marginal value, though Shreya and I have confirmed the code coming out of
expand looks good.  It's just that combine reconstitutes the operation via
mvconst_internal+and which looks cheaper.

When I was playing in this space earlier I definitely saw testsuite cases that
need this case handled to not regress with mvconst_internal removed.

This has spun in my tester on rv32 and rv64 and it's bootstrap + testing on my
BPI with a mere 23 hours to go.  Waiting on pre-commit testing to render a
verdict before moving forward.

gcc/
	* config/riscv/riscv.cc (synthesize_and): When profitable, use a three
	shift sequence to clear bits at both upper and lower bits rather than
	synthesizing the constant mask.