]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
sparc64: T5 PMU
authorbob picco <bpicco@meloft.net>
Tue, 16 Sep 2014 14:09:06 +0000 (10:09 -0400)
committerJiri Slaby <jslaby@suse.cz>
Fri, 31 Oct 2014 14:10:17 +0000 (15:10 +0100)
commit666892deef1df8c41eddec4df90136fd368b97df
tree5537f417737678d087de6f7d9fd0e58453c877e6
parent45a61adc8f2f3c62624e4d169618fa83aa63958b
sparc64: T5 PMU

commit 05aa1651e8b9ca078b1808a2fe7b50703353ec02 upstream.

The T5 (niagara5) has different PCR related HV fast trap values and a new
HV API Group. This patch utilizes these and shares when possible with niagara4.

We use the same sparc_pmu niagara4_pmu. Should there be new effort to
obtain the MCU perf statistics then this would have to be changed.

Cc: sparclinux@vger.kernel.org
Signed-off-by: Bob Picco <bob.picco@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
arch/sparc/include/asm/hypervisor.h
arch/sparc/kernel/hvapi.c
arch/sparc/kernel/hvcalls.S
arch/sparc/kernel/pcr.c
arch/sparc/kernel/perf_event.c