clk: at91: pll: fix input range validity check

clk: at91: pll: fix input range validity check

[ Upstream commit 6c7b03e1aef2e92176435f4fa562cc483422d20f ]

The PLL impose a certain input range to work correctly, but it appears that
this input range does not apply on the input clock (or parent clock) but
on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.

Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Jonas Andersson <jonas@microbit.se>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>