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dt-bindings: riscv: Add Nuclei UX900 compatibles
authorJunhui Liu <junhui.liu@pigmoral.tech>
Tue, 21 Oct 2025 09:41:37 +0000 (17:41 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 12 Nov 2025 17:06:56 +0000 (17:06 +0000)
commit66c2a3173cdaf7b776552203609f008c8709dd22
tree86dc21f8e0ebbe8945bec0b67f6778ce429afe3dtree | snapshot
parentc86ee66e14acb15d7d20b329ea49f751c9df8bc9commit | diff
dt-bindings: riscv: Add Nuclei UX900 compatibles

The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC.
It features a 64-bit architecture and dual-issue, 9-stage pipeline, with
lots of optional extensions including V, K, Zc, and more.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/riscv/cpus.yaml diff | blob | blame | history
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