RISC-V: Support cond vfsgnj.vv autovec patterns

RISC-V: Support cond vfsgnj.vv autovec patterns

This patch add combine patterns to combine vfsgnj.vv + vcond_mask
to mask vfsgnj.vv. For vfsgnjx.vv, it can not be produced in midend
currently. We will send another patch to take this issue.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*copysign<mode>_neg): Move.
	(*cond_copysign<mode>): New combine pattern.
	* config/riscv/riscv-v.cc (needs_fp_rounding): Extend.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-template.h: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: New test.