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riscv: dts: sophgo: add initial CV1812H SoC device tree
authorInochi Amaoto <inochiama@outlook.com>
Wed, 18 Oct 2023 23:18:53 +0000 (07:18 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Thu, 30 Nov 2023 12:40:36 +0000 (12:40 +0000)
commit681ec684a741ed3ac2c6b283b56245effa7a2c9d
tree68a934160da28a59cd0a84f8144246dcf1ebee9atree | snapshot
parentdd791b45c866b735601605b8dbceed4ab147db38commit | diff
riscv: dts: sophgo: add initial CV1812H SoC device tree

Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Acked-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/sophgo/cv1812h.dtsi [new file with mode: 0644] blob
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