]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add Andes 25 series pipeline description.
authorKuan-Lin Chen <rufus@andestech.com>
Wed, 12 Nov 2025 02:44:26 +0000 (10:44 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Wed, 12 Nov 2025 09:33:33 +0000 (17:33 +0800)
commit6947098a34ccc2f64ff52de88a136bc438091c10
treeff12b9f9cc59bd181742e98ffb840aae7930f9d5
parent845fb3b4a90fece0476a9061bf139c3290a5bab0
RISC-V: Add Andes 25 series pipeline description.

gcc/ChangeLog:

* config/riscv/andes-25-series.md: New file.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-25-series.
(RISCV_CORE): Add Andes 25-series cpu list.
* config/riscv/riscv-opts.h
(enum riscv_microarchitecture_type): Add andes_25_series_.
* config/riscv/riscv.cc: Add andes_25_tune_info.
* config/riscv/riscv.md: Add andes_25.
* doc/riscv-mcpu.texi: Regenerated for Andes cpu list.
* doc/riscv-mtune.texi: Regenerated for andes-25-series.
gcc/config/riscv/andes-25-series.md [new file with mode: 0644]
gcc/config/riscv/riscv-cores.def
gcc/config/riscv/riscv-opts.h
gcc/config/riscv/riscv.cc
gcc/config/riscv/riscv.md
gcc/doc/riscv-mcpu.texi
gcc/doc/riscv-mtune.texi