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git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add Andes 25 series pipeline description.
gcc/ChangeLog:
* config/riscv/andes-25-series.md: New file.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-25-series.
(RISCV_CORE): Add Andes 25-series cpu list.
* config/riscv/riscv-opts.h
(enum riscv_microarchitecture_type): Add andes_25_series_.
* config/riscv/riscv.cc: Add andes_25_tune_info.
* config/riscv/riscv.md: Add andes_25.
* doc/riscv-mcpu.texi: Regenerated for Andes cpu list.
* doc/riscv-mtune.texi: Regenerated for andes-25-series.