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clk: renesas: r9a08g046: Add SCIF{1..5} clocks and resets
authorBiju Das <biju.das.jz@bp.renesas.com>
Mon, 30 Mar 2026 13:23:41 +0000 (14:23 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 27 Apr 2026 09:42:09 +0000 (11:42 +0200)
commit6b99bb5e6ebec07815c0ad742862bafa386797ff
tree6b0624ec0660c153dbd34304af88d197e57b88actree | snapshot
parentc03f83f2a36291acca0b6638e91ab384fc319945commit | diff
clk: renesas: r9a08g046: Add SCIF{1..5} clocks and resets

Add SCIF{1..5} clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260330132349.149391-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a08g046-cpg.c diff | blob | blame | history
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