]> git.ipfire.org Git - thirdparty/linux.git/commit
iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
authorFangyu Yu <fangyu.yu@linux.alibaba.com>
Fri, 17 Apr 2026 14:07:46 +0000 (22:07 +0800)
committerJoerg Roedel <joerg.roedel@amd.com>
Mon, 11 May 2026 08:04:38 +0000 (10:04 +0200)
commit6c21eb174c6c7aebdecaf5c39e3100e6beb35faa
tree4d54799f76b4b482bc5941642277b35d42c156b0
parentf196a86687974cfcc1e8cade99ffca4605141860
iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
a way to tag mappings with page-based memory types. Encode memory type
via PBMT in RISC-V IOMMU PTEs:

  - IOMMU_MMIO   -> PBMT=IO
  - !IOMMU_MMIO && !IOMMU_CACHE -> PBMT=NC
  - otherwise    -> PBMT=Normal (PBMT=0)

Only touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
drivers/iommu/generic_pt/fmt/riscv.h