middle-end: make memory analysis for early break more deterministic [PR113135]

middle-end: make memory analysis for early break more deterministic [PR113135]

Instead of searching for where to move stores to, they should always be in
exit belonging to the latch.  We can only ever delay stores and even if we
pick a different exit than the latch one as the main one, effects still
happen in program order when vectorized.  If we don't move the stores to the
latch exit but instead to whever we pick as the "main" exit then we can
perform incorrect memory accesses (luckily these are trapped by verify_ssa).

We used to iterate over the conds and check the loads and stores inside them.
However this relies on the conds being ordered in program order.  Additionally
if there is a basic block between two conds we would not have analyzed it.

Instead this now walks from the preds of the destination basic block up to the
loop header and analyzes every block along the way.  As a later optimization we
could stop as soon as we've seen all the BBs we have conds for.  For now the
header will always contain the first cond, but this can change when we support
arbitrary control flow.

gcc/ChangeLog:

	PR tree-optimization/113135
	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
	dependency analysis.

gcc/testsuite/ChangeLog:

	PR tree-optimization/113135
	* gcc.dg/vect/vect-early-break_103-pr113135.c: New test.