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(parent: 5e354bf) | patch
AArch64: Improve codegen in AdvSIMD logs
authorPierre Blanchard <pierre.blanchard@arm.com>
Mon, 9 Dec 2024 15:54:34 +0000 (15:54 +0000)
committerWilco Dijkstra <wilco.dijkstra@arm.com>
Thu, 27 Feb 2025 17:51:10 +0000 (17:51 +0000)
commit72156cb90bb845eddf3acd59dd1599cec365942e
tree5147d1231148c36e1985d38f3abe3580f682793atree
parent5e354bf4e20ca3ccc15bda63c7b56ea0e97efa81commit | diff
AArch64: Improve codegen in AdvSIMD logs

Remove spurious ADRP and a few MOVs.
Reduce memory access by using more indexed MLAs in polynomial.
Align notation so that algorithms are easier to compare.
Speedup on Neoverse V1 for log10 (8%), log (8.5%), and log2 (10%).
Update error threshold in AdvSIMD log (now matches SVE log).

(cherry picked from commit 8eb5ad2ebc94cc5bedbac57c226c02ec254479c7)
sysdeps/aarch64/fpu/log10_advsimd.c diff | blob | blame | history
sysdeps/aarch64/fpu/log2_advsimd.c diff | blob | blame | history
sysdeps/aarch64/fpu/log_advsimd.c diff | blob | blame | history
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