RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2

RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2

Add asm dump check test for vec_duplicate + vor.vv combine to vor.vx,
with the GR2VR cost is 0, 1 and 2.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check
	for vor.vx combine.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>