RISC-V: Remove unnecessary option for scalar SAT_TRUNC testcase

RISC-V: Remove unnecessary option for scalar SAT_TRUNC testcase

After we create a isolated folder to hold all SAT scalar test,
we have fully control of what optimization options passing to
the testcase.  Thus, it is better to remove the unnecessary
work around for flto option, as well as the -O3 option for
each cases.  The riscv.exp will pass sorts of different optimization
options for each case.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_u_trunc-1-u16.c: Remove flto
	dg-skip workaround and -O3 option.
	* gcc.target/riscv/sat/sat_u_trunc-1-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-1-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-1-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-2-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-2-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-2-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-2-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-3-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-3-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-3-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-3-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-4-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-4-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-4-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-4-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-5-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-5-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-5-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-5-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-6-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-6-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-6-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_trunc-6-u8.c: Ditto.
	* gcc.target/riscv/sat/scalar_sat_unary.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>