]> git.ipfire.org Git - thirdparty/linux.git/commit
x86/resctrl: Fix memory bandwidth counter width for Hygon
authorXiaochen Shen <shenxiaochen@open-hieco.net>
Tue, 9 Dec 2025 06:26:50 +0000 (14:26 +0800)
committerBorislav Petkov (AMD) <bp@alien8.de>
Tue, 13 Jan 2026 15:44:26 +0000 (16:44 +0100)
commit7517e899e1b87b4c22a92c7e40d8733c48e4ec3c
treebff9ca6cd81b1ad7d49589c81992103f00a52c3d
parent6ee98aabdc700b5705e4f1833e2edc82a826b53b
x86/resctrl: Fix memory bandwidth counter width for Hygon

The memory bandwidth calculation relies on reading the hardware counter
and measuring the delta between samples. To ensure accurate measurement,
the software reads the counter frequently enough to prevent it from
rolling over twice between reads.

The default Memory Bandwidth Monitoring (MBM) counter width is 24 bits.
Hygon CPUs provide a 32-bit width counter, but they do not support the
MBM capability CPUID leaf (0xF.[ECX=1]:EAX) to report the width offset
(from 24 bits).

Consequently, the kernel falls back to the 24-bit default counter width,
which causes incorrect overflow handling on Hygon CPUs.

Fix this by explicitly setting the counter width offset to 8 bits (resulting
in a 32-bit total counter width) for Hygon CPUs.

Fixes: d8df126349da ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bsp_init helper")
Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251209062650.1536952-3-shenxiaochen@open-hieco.net
arch/x86/kernel/cpu/resctrl/core.c
arch/x86/kernel/cpu/resctrl/internal.h