]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
vfio/pci: Enable iowrite64 and ioread64 for vfio pci
authorRamesh Thomas <ramesh.thomas@intel.com>
Tue, 10 Dec 2024 13:19:37 +0000 (05:19 -0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 21 Feb 2025 13:01:26 +0000 (14:01 +0100)
commit758a5e1dc6db6d5ddf65d0b82b4caffc65efdb2a
treee309eb69d8615b624c5018b5dd4ec6dea915ae89
parent14a2a8ec50bcf90b087be66c30f43069402438e2
vfio/pci: Enable iowrite64 and ioread64 for vfio pci

[ Upstream commit 2b938e3db335e3670475e31a722c2bee34748c5a ]

Definitions of ioread64 and iowrite64 macros in asm/io.h called by vfio
pci implementations are enclosed inside check for CONFIG_GENERIC_IOMAP.
They don't get defined if CONFIG_GENERIC_IOMAP is defined. Include
linux/io-64-nonatomic-lo-hi.h to define iowrite64 and ioread64 macros
when they are not defined. io-64-nonatomic-lo-hi.h maps the macros to
generic implementation in lib/iomap.c. The generic implementation does
64 bit rw if readq/writeq is defined for the architecture, otherwise it
would do 32 bit back to back rw.

Note that there are two versions of the generic implementation that
differs in the order the 32 bit words are written if 64 bit support is
not present. This is not the little/big endian ordering, which is
handled separately. This patch uses the lo followed by hi word ordering
which is consistent with current back to back implementation in the
vfio/pci code.

Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20241210131938.303500-2-ramesh.thomas@intel.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/vfio/pci/vfio_pci_rdwr.c