RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4

RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4

This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 4.  Aka:

Form 4:
  #define DEF_SAT_U_ADD_IMM_FMT_4(T)                            \
  T __attribute__((noinline))                                   \
  sat_u_add_imm_##T##_fmt_4 (T x)                               \
  {                                                             \
    T ret;                                                      \
    return __builtin_add_overflow (x, 9, &ret) == 0 ? ret : -1; \
  }

DEF_SAT_U_ADD_IMM_FMT_4(uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add helper test macro.
	* gcc.target/riscv/sat_u_add_imm-13.c: New test.
	* gcc.target/riscv/sat_u_add_imm-14.c: New test.
	* gcc.target/riscv/sat_u_add_imm-15.c: New test.
	* gcc.target/riscv/sat_u_add_imm-16.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-13.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-14.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-15.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>