]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
net: dsa: mxl-gsw1xx: manually clear RANEG bit
authorDaniel Golle <daniel@makrotopia.org>
Tue, 9 Dec 2025 01:29:34 +0000 (01:29 +0000)
committerPaolo Abeni <pabeni@redhat.com>
Thu, 18 Dec 2025 11:53:21 +0000 (12:53 +0100)
commit7b103aaf0d564b83ee1d4bb532ee7ae36ed001ed
treefbe5fe27d4bb41ed7e3ccac81fa50b59d39836a6
parent651b253b80379b0eb3669405fcf50d4039dc7a0e
net: dsa: mxl-gsw1xx: manually clear RANEG bit

Despite being documented as self-clearing, the RANEG bit sometimes
remains set, preventing auto-negotiation from happening.

Manually clear the RANEG bit after 10ms as advised by MaxLinear.
In order to not hold RTNL during the 10ms of waiting schedule
delayed work to take care of clearing the bit asynchronously, which
is similar to the self-clearing behavior.

Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch family")
Reported-by: Rasmus Villemoes <ravi@prevas.dk>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://patch.msgid.link/76745fceb5a3f53088110fb7a96acf88434088ca.1765241054.git.daniel@makrotopia.org
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/dsa/lantiq/mxl-gsw1xx.c