RISC-V: Assign DWARF numbers to vector registers

RISC-V: Assign DWARF numbers to vector registers

This commit assigns DWARF register numbers to vector registers (v0-v31:
96..127) to implement RISC-V DWARF Specification version 1.0-rc4
(now in the frozen state):

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4

binutils/ChangeLog:

	* dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers
	96..127 to vector registers v0-v31.

gas/ChangeLog:

	* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support
	vector registers.
	* testsuite/gas/riscv/dw-regnums.s: Add vector registers to the
	DWARF register number test.
	* testsuite/gas/riscv/dw-regnums.d: Likewise.