aarch64: Add support for sme2.1 zero instructions.

aarch64: Add support for sme2.1 zero instructions.

This patch adds support for following sme2.1 zero instructions and
the spec is available here [1].

1. ZERO (single-vector).
2. ZERO (double-vector).
3. ZERO (quad-vector).

The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler
for most of the sme and sve instructions. But for few of the sme2.1
zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory.
To address this a bit "F_VG_REQ" is introduced in this patch, on setting
F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept
instruction operand only having VECTOR GROUP symbols.

[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en