x86: drop a few excess AVX512VL from opcode table

x86: drop a few excess AVX512VL from opcode table

In commit 24187fb9c0d0 ("x86/APX: extend SSE2AVX coverage") I apparently
went a little to far with AVX512VL uses:
- PEXTRQ and PINSRQ are AVX512DQ alone, despite using 128-bit (XMM)
  registers,
- SSE41DQ is used for only PEXTRD and PINSRD, falling in the same
  category.

With the SSE41DQ observation above, also simplify Disp8MemShift handling
there: No need to override it in the insn template, as long as the
manufacturing template specifies it correctly.

Note that the AVX512DW form of PINSRQ also had a stray "AVX" CPU specifier
on it. Make this disappear by templatizing via a new SSE41DQ64
manufacturing template (covering PEXTRQ and PINSRQ, paralleling SSE41DQ).