aarch64: Annotate fcvtn pattern for vec_concat with zeroes

aarch64: Annotate fcvtn pattern for vec_concat with zeroes

Using the define_substs in aarch64-simd.md this is a straightforward annotation to remove
a redundant fmov insn.

So the codegen goes from:
foo_d:
        fcvtn   v0.2s, v0.2d
        fmov    d0, d0
        ret

to the simple:
foo_d:
        fcvtn   v0.2s, v0.2d
        ret

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_): Rename to...
	(aarch64_float_truncate_lo_<mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/float_truncate_zero.c: New test.