aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891]

aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891]

aarch64_expand_vector_init contains some divide-and-conquer code
that tries to load the odd and even elements into 64-bit registers
and then ZIP them together.  On big-endian targets, the even elements
are more significant than the odd elements and so should come second
in the ZIP.

This fixes many execution failures on aarch64_be-elf, including
gcc.c-torture/execute/pr28982a.c.

gcc/
	PR target/118891
	* config/aarch64/aarch64.cc (aarch64_expand_vector_init): Fix the
	ZIP1 operand order for big-endian targets.

(cherry picked from commit cb2b5471516c3c469f65d927a2a30eb15357e429)