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aarch64: Add a VNx1TI mode
authorRichard Sandiford <richard.sandiford@arm.com>
Tue, 5 Dec 2023 10:11:27 +0000 (10:11 +0000)
committerRichard Sandiford <richard.sandiford@arm.com>
Tue, 5 Dec 2023 10:11:27 +0000 (10:11 +0000)
commit80fc055cf00fee4b1f9f19f77c8880b12226e086
tree2bea0e571c02966011cf019454625d14c030cd04tree
parent084122adb5792a9c8e7f7876e2c1d59ba80c228bcommit | diff
aarch64: Add a VNx1TI mode

Although TI isn't really a native SVE element mode, it's convenient
for SME if we define VNx1TI anyway, so that it can be used to
distinguish .Q ZA operations from others.  It's purely an RTL
convenience and isn't (yet) a valid storage mode.

gcc/
* config/aarch64/aarch64-modes.def: Add VNx1TI.
gcc/config/aarch64/aarch64-modes.def diff | blob | blame | history
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