]> git.ipfire.org Git - thirdparty/kernel/linux.git/commit
drm/amd/display: Correct slice width calculation for YCbCr420
authorRelja Vojvodic <rvojvodi@amd.com>
Wed, 17 Sep 2025 16:30:51 +0000 (12:30 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 13 Oct 2025 18:14:31 +0000 (14:14 -0400)
commit81557c96c8a171b5d2500662d4d62f27ab6bad23
tree01fe8a834e9260428c1869a0dc31d4c0c8aa79fe
parent0975c4deb6c2a5abc1865f0ba5502b10c87b7d27
drm/amd/display: Correct slice width calculation for YCbCr420

[Why]
-OVT compliance testing for 5120x2880p300Hz YCbCr420 was failing due to
incorrect slice width being calculated

[How]
-Ensure slice width is divisible by 2 for 420 to comply with spec

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Relja Vojvodic <rvojvodi@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
drivers/gpu/drm/amd/display/dc/dsc/dsc.h
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c