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clk: rockchip: rk3588: Add PLL rate for 1500 MHz
authorAlexander Shiyan <eagle.alexander923@gmail.com>
Tue, 8 Apr 2025 06:46:12 +0000 (09:46 +0300)
committerHeiko Stuebner <heiko@sntech.de>
Thu, 10 Apr 2025 12:28:14 +0000 (14:28 +0200)
commit831a8ac72264426ccd0ee5d2b0d74491ea7d2bfb
tree1567f6922908da0a9d57fb734d558c94ba58d569tree | snapshot
parent0af2f6be1b4281385b618cb86ad946eded089ac8commit | diff
clk: rockchip: rk3588: Add PLL rate for 1500 MHz

At least one RK3588 clock (CPLL) uses 1.5 GHz, so let's add
that frequency to the PLL table.

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Link: https://lore.kernel.org/r/20250408064612.41359-1-eagle.alexander923@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3588.c diff | blob | blame | history
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