[to-be-committed,RISC-V] Improve variable bit set for rv64

[to-be-committed,RISC-V] Improve variable bit set for rv64

Another case of being able to safely use bset for 1 << n.  In this case
the (1 << n)  is explicitly zero extended from SI to DI.  Two things to
keep in mind.  The (1 << n) is done in SImode.  So it doesn't directly
define bits 32..63 and those bits are cleared by the explicit zero
extension.  Second if N is out of SImode's range, then the original
source level construct was undefined.

Thus we can use bset with x0 as our source input.

I think this testcase was from the RAU team.  It doesn't immediately
look like something from SPEC, but that's where they were primarily focused.

This has been through Ventana's CI system in the past.  I've also
recently added zbs testing to my own tester and naturally this passed
there as well.  I'll wait for the pre-commit CI to do its thing before
moving forward.  The plan would be to commit after passing.

gcc/
	* config/riscv/bitmanip.md (bsetdi_2): New pattern.

gcc/testsuite/

	* gcc.target/riscv/zbs-zext-2.c: New test.