RISC-V: Combine vec_duplicate + vmsltu.vv to vmsltu.vx on GR2VR cost

RISC-V: Combine vec_duplicate + vmsltu.vv to vmsltu.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vmsltu.wv to the
vmsltu.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have asm code like below, GR2VR cost is 0.

Before this patch:
  11       beq a3,zero,.L8
  12       vsetvli a5,zero,e32,m1,ta,ma
  13       vmv.v.x v2,a2
  ...
  16   .L3:
  17       vsetvli a5,a3,e32,m1,ta,ma
  ...
  22       vmsltu.wv v1,v2,v3
  ...
  25       bne a3,zero,.L3

After this patch:
  11       beq a3,zero,.L8
  ...
  14    .L3:
  15       vsetvli a5,a3,e32,m1,ta,ma
  ...
  20       vmsltu.wx v1,a2,v3
  ...
  23       bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*pred_cmp_swapped<mode>_scalar):
	Add new pattern to match vec_dup > vec for vmsltu.
	* config/riscv/predicates.md (comparison_swappable_operator):
	Add new iterator for above pattern
	* config/riscv/riscv-protos.h (expand_vx_cmp_vec_dup_vec): Add
	new func to emit vmsltu.vx.
	* config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Add new
	func to convert cmp code to swapped, like gtu to ltu.
	(expand_vx_cmp_vec_dup_vec): Add new func decl.

Signed-off-by: Pan Li <pan2.li@intel.com>