arm64: dts: imx8mp: Add pclk clock and second power domain for the ISP

arm64: dts: imx8mp: Add pclk clock and second power domain for the ISP

The ISP HDR stitching registers are clocked by the pixel clock, which is
gated by the MIPI_CSI2 power domain. Attempting to access those
registers with the clock off locks up the system. Fix this by adding the
pclk clock and the MIPI_CSI2 secondary power domain.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>