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RISC-V: Support TU for integer ternary OP[PR110964]
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Thu, 10 Aug 2023 09:21:46 +0000 (17:21 +0800)
committerPan Li <pan2.li@intel.com>
Thu, 10 Aug 2023 12:29:47 +0000 (20:29 +0800)
commit887f13916b18f46b563d527ad5001c6384e44a60
tree450ff376aae54ff84db00b0a20d3e0849cf9cfc3tree
parent9b8ebdb60c463fa3641692a21ca0ce24fba89260commit | diff
RISC-V: Support TU for integer ternary OP[PR110964]

PR target/110964

gcc/ChangeLog:
PR target/110964
* config/riscv/riscv-v.cc (expand_cond_len_ternop): Add integer ternary.

gcc/testsuite/ChangeLog:
PR target/110964
* gcc.target/riscv/rvv/autovec/pr110964.c: New test.
gcc/config/riscv/riscv-v.cc diff | blob | blame | history
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c [new file with mode: 0644] blob
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