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dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in...
authorYangyu Chen <cyy@cyyself.name>
Tue, 3 Feb 2026 17:21:48 +0000 (01:21 +0800)
committerThomas Gleixner <tglx@kernel.org>
Wed, 4 Feb 2026 10:13:58 +0000 (11:13 +0100)
commit889588d750506d86ba16ae3b968b5ffc5937d5f8
treeaf742c6085b43503f312650ee459aa6aaf6d936dtree
parent42e025b719c128bdf8ff88584589a1e4a2448c81commit | diff
dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC

In PLIC, interrupt source 0 is reserved and should not be used.
Therefore, the valid interrupt sources are from 1 to riscv,ndev
inclusive.

Update the documentation to clarify this point.

[ tglx: Fixup subject prefix ]

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml diff | blob | blame | history
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