[AArch64] Fix wrong-code bug in right-shift SISD patterns

[AArch64] Fix wrong-code bug in right-shift SISD patterns

	Backport from mainline
	2015-02-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/aarch64/aarch64.md (*aarch64_lshr_sisd_or_int_<mode>3):
	Mark operand 0 as earlyclobber in 2nd alternative.
	(1st define_split below *aarch64_lshr_sisd_or_int_<mode>3):
	Write negated shift amount into QI lowpart operand 0 and use it
	in the shift step.
	(2nd define_split below *aarch64_lshr_sisd_or_int_<mode>3): Likewise.

	* gcc.target/aarch64/sisd-shft-neg_1.c: New test.

From-SVN: r220863