LoongArch: Add support for the TARGET_MODES_TIEABLE_P vectorization type.

LoongArch: Add support for the TARGET_MODES_TIEABLE_P vectorization type.

v1->v2:
Add the TARGET_MODES_TIEABLE_P function description and analyze the
reasons for the cost change of Subreg type rtx after supporting
vectorization.

This hook returns true if a value of mode mode1 is accessible in mode
mode2 without copying. On LA, for vector types V4SF and V8SF, the lower
128 bit data can be shared. After adding vector support in this hook,
the cost of type conversion for the subreg operation from the V4SF to
the V8SF registers can be made zero, and some rtx optimization
operations can be completed in the combine traversal. The comparison
of the backend support vectors before and after is as follows:

support before:

(insn 7 4 9 2 (set (reg:V8SF 82 [ _6 ])
        (subreg:V8SF (reg:V4SF 86 [ aD.7906 ]) 0))
(insn 9 7 10 2 (set (reg:V8SF 80 [ _4 ])
        (plus:V8SF (reg:V8SF 82 [ _6 ])
            (reg:V8SF 82 [ _6 ])))

===>

support after:

(insn 9 7 10 2 (set (reg:V8SF 80 [ _4 ])
        (plus:V8SF (subreg:V8SF (reg:V4SF 86 [ aD.7906 ]) 0)
            (subreg:V8SF (reg:V4SF 86 [ aD.7906 ]) 0)))

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_modes_tieable_p):
	Add support for vector conversion.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/vector/lasx/vect-extract-256-128.c:
	After supporting the vectorized type corresponding to subreg in
	the backend, the cost of rtx becomes 0. In fwprop1 pass,
	memory-loaded rtx cannot be propagated to this insn, which leads
	to xvld not being optimized into vld instructions.
	* gcc.target/loongarch/vect-mode-tieable.c: New test.