RISC-V: Add FRM and rounding mode operand into floating point intrinsics

RISC-V: Add FRM and rounding mode operand into floating point intrinsics

This patch is adding rounding mode operand and FRM_REGNUM dependency
into floating-point instructions.

The floating-point instructions we added FRM and rounding mode operand:
1. vfadd/vfsub
2. vfwadd/vfwsub
3. vfmul
4. vfdiv
5. vfwmul
6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac
7. vfsqrt
8. floating-point conversions.
9. floating-point reductions.
10. floating-point ternary.

The floating-point instructions we did NOT add FRM and rounding mode
operand:
1. vfabs/vfneg/vfsqrt7/vfrec7
2. vfmin/vfmax
3. comparisons
4. vfclass
5. vfsgnj/vfsgnjn/vfsgnjx
6. vfmerge
7. vfmv.v.f

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (enum frm_field_enum): New enum.
	* config/riscv/riscv-vector-builtins.cc
	(function_expander::use_ternop_insn): Add default rounding mode.
	(function_expander::use_widen_ternop_insn): Ditto.
	* config/riscv/riscv.cc (riscv_hard_regno_nregs): Add FRM REGNUM.
	(riscv_hard_regno_mode_ok): Ditto.
	(riscv_conditional_register_usage): Ditto.
	* config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto.
	(FRM_REG_P): Ditto.
	(RISCV_DWARF_FRM): Ditto.
	* config/riscv/riscv.md: Ditto.
	* config/riscv/vector-iterators.md: split no frm and has frm operations.
	* config/riscv/vector.md (@pred_<optab><mode>_scalar): New pattern.
	(@pred_<optab><mode>): Ditto.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>