RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv

RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv

The div of rvv has not such insn v2 = div (vec_dup (x), v1), thus
the generated rtl like that hit the unreachable assert when
expand insn.  This patch would like to remove op div from
the binary op form (vec_dup (x), v) to avoid pattern matching
by mistake.

No new test introduced as pr33576.c covered already.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Leverage vdup_v and v_vdup
	binary op for different patterns.
	* config/riscv/vector-iterators.md: Add vdup_v and v_vdup
	binary op iterators.

Signed-off-by: Pan Li <pan2.li@intel.com>